During the ASTC conference held in Marina Bay Sands Convention Centre – Singapore, the 7th and 8th of November 2019, Unity Semiconductor will present a paper entitled :
Process Control solutions for Advanced Packaging
You can already read below an abstract of what we will be treated during this conference.
The conference provides a platform for business leaders and technology experts in the ATE semiconductor as well as EDA supply chain ecosystem to share their insights and perspectives in these areas of interests for an active, engaging and thought-provoking discussion session.
Authors: Dr Dario Alliata
Content:
With the explosion of cost and complexity at the most advanced front-end silicon technology nodes, alternatives ways are explored to keep the product manufacturing profitable. Device performances are continuously improved to face the demand for High Performance Computing and Artificial Intelligence.
Advanced Packaging has become a key differentiator for achieving next-generation requirements, and thereby continued sustainability [1], in the semiconductor industry. Since early 2000, when the Embedded Wafer Level Balling (EWLB) approach was introduced, several flavors of packaging based on fan-out have been presented (INFO, EMIB, SWIFT). With a CARG > 19%, the High-Density wafer level Fan-Out is the most promising market, with more and more players moving away their packaging from wire bonding [2].
Despite the maturity of the advance packaging industry, we are still in an era where several issues can put at risk the process chain. Therefore, the need of process control solutions with systems as much as possible capable of covering inspection and metrology needs at 360 degree on the very same platform. Key process steps like molding and passivation in WLFO or TSV etch in 3D stacking are still requiring major control. RDL entering the sub-micron territory also represents a challenge in term of metrology & inspection.
In this paper, we are presenting our progress in developing solutions for the Advanced packaging arena by combining inspection and metrology strategies to identify the root cause of the yield loss. Multiple inspection techniques are used to identify and classify visible and invisible defects at each surface of the wafer. Complementary metrology techniques are used to secure the process development and high volume manufacturing. Customizing the solution is the new way to secure the manufacturing.
[1] Carballo, J.-A. & Chang, W.-T.J. & Gargini, P.A. & Kahng, A.B. & Nath, S. (2014) ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap. ICCD 2014 32nd IEEE International Conference on Computer Design, pp. 139-146.
[2] Fan-Out packaging: Technology and Market Trends 2019 report, Yole Development, November
About the ASTC Event :
ADVANCED PACKAGING AND SYSTEM LEVEL TEST FOR THE ERA OF HIGH-PERFORMANCE COMPUTING (HPC) AND ARTIFICIAL INTELLIGENCE (AI)
The next revolutionary innovation in advanced packaging and system test to meet the quest of size, cost, performance and manufacturability is discussed at this forefront forum for the megatrend of HPC&AI as well as 5G.
What is the market size of such drivers in fueling these disruptive packaging and testing technologies? What are the key features in advanced packaging and system testing technology is in play enabling competitive business capture? What are the implications of the demand of such new disruptive technologies in the ATE space offers to Southeast Asia Foundries, IDM ad OSATs players?
The conference also features latest innovative solutions through exhibit booths display.
To get more information about this event, please visit the IMAPS website : https://www.semi.org